This invention relates to binary counters and more particularly to a high speed binary up/down (U/D) counter implemented with CMOS technology having a plurality of multi-bit stages which may be concatenated in multiple sections.
Binary ripple time counters are well known in the prior art. They have been implemented utilizing CMOS technologies but have the disadvantage of the carry rippling through each stage of the binary counter which takes a considerable amount of time. In order to decrease this carry ripple time, look-ahead circuits comprising AND or NAND gates have been used; however, such gates have required a significant amount of die area as the number of counter stages increases thereby increasing the number of inputs to look-ahead gates. In addition, the time delays associated with the increased gating reduces the counting rate of such a binary counter.
A CMOS transmission gate look-ahead carry circuit has been utilized in a CMOS synchronous binary counter as described in U.S. Pat. No. 3,943,378, inventor R. R. Beutler which requires only a small amount of die area. However, this is a counter with ripple carry employing a carry pass structure which looks at the previous stage employing toggle flip-flops to effect a count; a compromise is made between obtaining a higher speed binary counter and minimizing usage of the die area.
In U.S. Pat. No. 4,037,085 to inventor Kazuo Minorikawa a binary counter is shown which may have its count advanced at a high speed in accordance with a control signal. Each stage senses its own current state in determining what happens in the next stage; however, in a continuous counting operation considerable time is required in this invention for the carry signal to ripple from one stage to the next stage.
A CMOS binary up/down counter is described in U.S. Pat. No. 4,611,337 to Michael W. Evans. A counter stage comprises an exclusive-OR gate, a D-type flip-flop and a multiplexer interconnected to operate in accordance with a clock signal and a U/D control signal. The fabrication of a multiplexer in CMOS technology is simpler than such implementation in bipolar transistor-transistor-logic (TTL) technology. However, when cascading a plurality of these CMOS up/down counter stages to form an N stage counter with reasonable counting speed, each stage requires a multi-input AND gate having the number of inputs equal to its stage position in the counter, with the last stage having an N input AND gate; this results in the inefficient use of die area of a CMOS integrated circuit.
An improvement in the art of high speed CMOS binary counters is described in U.S. Pat. No. 4,759,043 entitled CMOS Binary Counter filed by Edward T. Lewis and assigned to the present assignee. In such CMOS binary counter each 4-bit counter section performs a counting function through a successive process of additions of a lowest order stage carry input, and each bit stage within a 4-bit section uses the current state of each stage to determine what happens in the next stage. A carry-forward generator instead of a carry-generation network provides a carry-forward signal to the next 4-bit counter section with a worse case delay of only a 2-input gate delay thereby enabling high speed operation.